VLSI Part-1 (ECE-3002)

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SYLLABUS (This Document contains Module 1,2)


Module:1
MOS Transistor Theory
5 hours
SLO: 2
I-V Characteristics, C-V Characteristics, Non-ideal I-V Effects of MOS Transistors

Module:2
CMOS Logic
5 hours
SLO: 2
Basic Gates, Compound Gates, Transmission Gates Based Combinational and Sequential Logic Design

Module:3
CMOS Circuit characterization and Performance Estimation
8 hours
SLO: 2
DC Transfer Characteristics of CMOS Inverter, Circuit Characterization and Performance Estimation: Delay Estimation, Logical Effort and Transistor Sizing. Power Dissipation: Static & Dynamic Power Dissipation.

Module:4
CMOS Fabrication and Layout
5 hours
SLO: 5
CMOS Process Technology N-well, P-well Process, Stick Diagram for Boolean Functions using Euler Theorem, Layout Design Rule

Module:5
CMOS Combinational Circuit Design
7 hours
SLO: 5
Static CMOS, Ratioed Logic, CascodeVoltage Switch Logic, Dynamic Circuits,  Pass Transistor Circuits

Module:6
CMOS Sequential Circuit Design
7 hours
SLO: 5
Conventional CMOS Latches and Flip Flops, Pulsed Latches, Resettable and Enabled Latches and Flip Flops
Module:7
Sub System Design
6 hours
SLO: 5
Single-bit Adder, CLAAdder, Carry-propagate Adder, Magnitude Comparator,  Barrel Shifter, Signed and Unsigned multiplier.





CLICK HERE TO VIEW MODULE-1





CLICK HERE TO VIEW MODULE-2




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